CDC Cyber Totally Explained

Everything about The Cdc Cyber totally explained

The CDC Cyber range of mainframe/super-computers were the primary products of Control Data Corporation (CDC) during the 1970's and 1980's.

Models

The Cyber line included five very different models of computer:

The 70 and 170 series based on the architecture of the CDC 6600 and CDC 7600
The 180 series developed by a team in Canada
The 200 series based on the CDC STAR-100
The CYBERPLUS or Advanced Flexible Processor (AFP)
The Cyber-18 minicomputer based on the CDC 1700

Primarily aimed at large office applications instead of the traditional supercomputer tasks, some of the Cyber machines nevertheless included basic vector instructions for added performance in "traditional" CDC roles.

CDC Cyber 70 and 170 series

The Cyber 70 and 170 architectures were successors to the earlier CDC 6600 and CDC 7600 series and therefore shared almost all of the earlier architecture's characteristics. The Cyber-70 series was a minor upgrade from the earlier systems. The Cyber-170 series represented CDCs move from discrete electronic components and core memory to integrated circuits and semiconductor memory. The Cyber-170/700 series was a late-1970s refresh of the Cyber-170 line.
   The central processor (CPU) and central memory (CM) operated in units of 60-bit words. In CDC lingo, the term "byte" referred to 12-bit entities (which coincided with the word size used by the peripheral processors). Characters were six bits, operation codes were six bits, and central memory addresses were 18 bits. Central processor instructions were either 15 bits or 30 bits. The 18-bit addressing inherent to the Cyber 170 series imposed a limit of 262,144 (256K) words of main memory, which was semiconductor memory in this series. The central processor had no I/O instructions, relying upon the peripheral processor (PP) units to do I/O.
   A Cyber 170-series system consisted of one or two CPUs that ran at either 25 or 40 MHz, and was equipped with 10, 14 or 20 peripheral processors (PP), and up to 24 high-performance channel controllers for high-speed I/O. Due to the relatively slow memory reference times of the CPU (in some models, memory reference instructions were slower than floating point divides), the higher end CPUs (for example, Cyber-74, Cyber-76, Cyber-175, and Cyber-176) were equipped with 8 words of high-speed memory used as an instruction cache. Any loop that fit into the cache (which was sometimes called in-stack) would run without referencing main memory for instruction fetch. The lower-end models didn't contain an instruction stack. However since up to four instructions were packed into each 60-bit word, some degree of prefetching was inherent in the design.
   As with predecessor systems, the Cyber 170 series had eight 18-bit address registers (A0 through A7), eight 18-bit index registers (B0 through B7), and eight 60-bit operand registers (X0 through X7). Seven of the A registers were tied to their corresponding X register. Setting A1 through A5 read that address and fetched it into the corresponding X1 through X5 register. Likewise, setting register A6 or A7 wrote the corresponding X6 or X7 register to central memory at the address written to the A register. A0 was effectively a scratch register.
   The higher end CPUs consisted of multiple functional units (for example, shift, increment, floating add) which allowed some degree of parallel execution of instructions. This parallelism allowed assembly programmers to minimize the effects of the system's slow memory fetch time by pre-fetching data from central memory well before that data was needed. By interleaving independent instructions between the memory fetch instruction and the instructions manipulating the fetched operand, the time occupied by the memory fetch could be used for other computation. With this technique, coupled with the handcrafting of tight loops that fit within the instruction stack, a skilled Cyber assembly programmer could write extremely efficient code that made the most of the power of the hardware.
   The peripheral processor subsystem used a technique known as barrel and slot to share the execution unit; each PP had its own memory and registers, but the processor (the slot) itself executed one instruction from each PP in turn (the barrel). This is a crude form of hardware multiprogramming. The peripheral processors had 4096 bytes of 12-bit memory words and an 18-bit accumulator register. Each PP had access to all I/O channels and all of the system's central memory (CM) in addition to the PP's own memory. The PP instruction set lacked, for example, extensive arithmetic capabilities and didn't run user code; the peripheral processor subsystem's purpose was to process I/O and thereby free the more powerful central processor unit(s) to running user computations.
   A feature of the 'lower Cyber' CPUs was the Compare Move Unit (CMU). It provided four additional instructions intended to aid text processing applications. In an unusual departure from the rest of the 15- and 30-bit instructions, these were 60-bit instructions (3 actually used all 60 bits, the other used 30 bits, but its alignment required 60 bits to be used). The instructions were move a short string, move a long string, compare strings, and compare a collated string. They operated on 6-bit fields (numbered 1 through 10) in central memory. For example, a single instruction could specify "move the 72 character string starting at word 1000 character 3 to location 2000 character 9". The CMU hardware wasn't included in the higher-end Cyber CPUs, because handcoded loops could run as fast or faster than the CMU instructions.
   Later systems typically ran CDC's NOS (Network Operating System). Version 1 of NOS continued to be updated until about 1981; NOS version 2 was released early 1982. Besides NOS, the only other operating systems commonly used on the 170 series was NOS/BE or its predecessor SCOPE, a product of CDC's Sunnyvale division. These operating systems provided time sharing of batch and interactive applications. The predecessor to NOS was KRONOS which was in common use up until 1975 or so. Due to the strong dependency of developed applications on the particular installation's character set, many installations chose to run the older operating systems than convert their applications. Other installations would patch newer versions of the operating system to use the older character set to maintain application compatibility. Desktop CYBER emulates CDC Cyber 70 and 170 series mainframes in software running on modern desktop PCs.

CDC Cyber 180 series

As the computing world standardized to an eight-bit byte size, CDC customers started pushing for the Cyber machines to do the same. The result was a new series of systems that could operate in both 60- and 64-bit modes. The 64-bit operating system was called NOS/VE, and supported the virtual memory capabilities of the hardware. The older 60-bit operating systems, NOS and NOS/BE, could run in a special address space for compatibility with the older systems.
   The true 180-mode machines were microcoded processors that could, and did, support both instruction sets simultaneously. Their hardware was completely different from the earlier 6000/70/170 machines. The small 170-mode exchange package was mapped into the much larger 180-mode exchange package; within the 180-mode exchange package, there was a VMID—virtual machine identifier—that determined whether the 8/16/64-bit twos complement 180 instruction set or the 12/60-bit ones complement 170 instruction set was executed.
   There were 3 true 180s in the initial lineup, codenamed P1, P2, P3. P2 & P3 were larger water-cooled designs from Arden Hills. The P1 was a novel air-cooled, 60-board cabinet designed by a group in Toronto; the P1 ran on 60 Hz current (no motor-generator sets needed). A fourth high-end 180 codenamed THETA was also under development.
   The 180's were initially marketed as 170/8xx machines with no mention of the new 8/64-bit system inside. However, the primary control program was a 180-mode program known as EI (Environmental Interface). The 170 operating system (NOS) utilized a single, large, fixed page within the main memory. There were a few clues that an alert user could pick up on, such as the "building page tables" message that flashed on the operator's console at startup and deadstart panels with 16 (instead of 12) toggle switches per PP word on the P2 & P3.
   The peripheral processors in the true 180s were always 16-bit machines with the sign bit determining whether a 16/64 bit or 12/60 bit PP instruction was being executed. The single word I/O instructions in the PPs were always 16-bit instructions, so at deadstart the PPs could set up the proper environment to run both EI plus NOS & the customer's existing 170-mode software. To hide this process from the customer, earlier in the 1980s CDC had ceased distribution of the source code for its DDS (Deadstart Diagnostic Sequence) package and turned it into the proprietary CTI (Common Tests & Initialization) package.
   The initial 170/800 lineup was: 170/825 (P1), 170/835 (P2), 170/855 (P3), 170/865 and 170/875. The 825 was released initially after some delay loops had been added to its microcode; it seemed the design folks in Toronto had done a little too well and it was too close to the P2 in performance. The 865 and 875 models were revamped 170/760 heads (1 or 2 processors with 6600/7600-style parallel functional units) with larger memories. The 865 used normal 170 memory; the 875 took its faster main processor memory from the Cyber 205 line.
   A year or two after the initial release, CDC announced the 800-series' true capabilities to its customers, and the true 180s were relabeled as the 180/825 (P1), 180/835 (P2), and 180/855 (P3). At some point the model 815 was introduced with the delayed microcode and the faster microcode was restored to the model 825. Eventually the THETA was released as the Cyber 990.

CDC Cyber 200 series

In 1974 CDC introduced their STAR architecture. The STAR was an entirely new 64-bit design with vector processing instructions added for high performance on math tasks. The machine also supported virtual memory. The STARs vector pipeline was a memory to memory pipe, which supported vector lengths of up to 64k (65,536) elements. Unfortunately, the latencies of the vector pipeline were very long, so peak speed was only approached when very long vectors were used. The scalar processor was relatively slow in comparison to the CDC 7600. As such, the original STAR proved to be a great disappointment when it was released. (See: Amdahls Law.) However many of its problems seemed solvable.
   In the late 1970s CDC addressed some of these issues with the Cyber 203, the new naming in keeping with their new branding, and perhaps to distance itself from the STAR's failure. The Cyber-203 contained redesigned scalar processing and loosely coupled I/O design, but retained the STARs vector pipeline.
   In 1979, the Cyber 205 replaced the STAR vector pipeline with redesigned vector pipelines - both scalar and vector units utilized ECL IC technology with freon cooling. Cyber-205 systems were available with two or four vector pipelines, with the 4-pipe version theoretically delivering 64-bit 400 MFLOPs and reaching as high as 800 MFLOPs with 32-bit operations - in practice, these speeds were rarely seen in practice other than handcrafted assembly language. The ECL IC's contained approximately 20-30 gates of logic, with the clock tree networks being tuned by hand-crafted tuning of coax clock networks. It is worth noting that the instruction set would be considered V-CISC (very complex instruction set) in comparison to processors of today - many specialized operations were included that would facilitate hardware searches, matrix mathematics, and special instructions that would enable decryption (for government agencies). This architecture evolved into the ETA10 as the design team spun off into ETA Systems in 1983.
   Also there was a CYBER 250 which was scheduled for release in 1987 priced at $20 Million, it was later renamed the ETA30 (once ETA Systems was re-absorbed back into CDC).

CDC CYBERPLUS/AFP

At least 21 CYBERPLUS (aka Advanced Flexible Processor, AFP) multiprocessor installations were operational in 1986. These Parallel Processing Systems include from 1 to 256 CYBERPLUS processors providing 250 MFLOPS each, which are connected to an existing CYBER system via a direct memory interconnect architecture (MIA), this was available on NOS 2.2 for the CYBER 170/835, 845, 855 and 180/990 models. Each CYBERPLUS is a 16-bit processor with optional 64-bit floating point capabilities and has 256 K or 512 K words of 64-bit memory. Each physical CYBERPLUS processor unit was:

348 cm wide (465 cm with floating point unit)

161 cm deep

490 cm high

1000 kg weight Software that was bundled with the CYBERPLUS was:

system software

FORTRAN cross compiler

MICA (Machine Instruction Cross Assember)

Load File Builder Utility

ECHOS (simulator)

Debug facility

Dump utility

Dump analyzer utility

Maintenance software One known installation was at the Gesellschaft fur Trendanalysen (GFTA) in Germany
A fully configured 256 processor CYBERPLUS system would have a theoretical performance of 64 GFLOPS and weighed 256 tonnes!

Cyber-18

A 16-bit minicomputer which was a successor to the CDC 1700 minicomputer. It was mostly used in real-time environments. One noteworthy application is that the Cyber-18 formed the basis of the 2550 - a communications processor used by CDC 6000 series and Cyber-70/Cyber-170 mainframes. The 2550 was a product of CDC's Communications Systems Division, in Santa Ana, California (STAOPS). STAOPS also produced another communication processor (CP), used in networks hosted by IBM mainframes. This M1000 CP, later renamed C1000, came from an acquisition of Marshall MDM Communications.
The Cyber-18 was generally programmed in Pascal and assembly language; FORTRAN, BASIC, and RPG II were also available. Operating systems included RTOS (Real-Time Operating System), MSOS 5 (Mass Storage Operating System), and TIMESHARE 3 (time-sharing system).
"Cyber 18-17" was just a new name for the System 17, based on the 1784 processor. Other Cyber 18s (Cyber 18-05, 18-10, 18-20, and 18-30) had microprogrammable processors with up to 128K words of memory, four additional general registers, and an enhanced instruction set. The Cyber 18-30 had dual processors.

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